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There is a myth running around that the PentiumPro, Pentium II (and now PentiumIII) are RISC chips. This isn't realistic -- but it is becoming common enough that it should be addressed.
What is RISC
RISC stands for Reduced Instruction Set Computing. This is a design philosophy where you reduce the COMPLEXITY of the instruction set, which will reduce the amount of space (and time) it takes to implement the instruction set (not the count) -- then you take that saved time, space, money and so on. You use those various savings to implement a better chip (engineering is about tradeoffs). The way you implement the better chip is that you get the chip out on a more "modern" manufacturing process sooner (which means faster and lower power), you get the chip to market faster, you take less space on the chip and use the space savings for other things like Pipelining, Out-of-order execution, superscalar (multiple units), branch prediction, cache, and so on. The chip also requires less heat, size, costs less to make and so on. So RISC is about knowing what to leave out.
What RISC is NOT
What RISC does NOT stand for is reduced instruction set COUNT. Cutting the number of instructions has basically nothing to do with RISC. Sure the fewer instructions you have to implement the less complex the instruction set can be, and so some RISC implementations do trim a lot of instruction out, but that not the primary goal (just a secondary way to achieve it). In fact, many times simplifying the instruction sets complexity requires adding more instructions.
For example:
Older CISC processors have an instruction that moves data around (MOV). It MOV's either from registers to memory, from memory to registers, from registers to registers, and from memory to memory. It is a nightmare to implement this one instruction and it is very complex (in size, space and time to implement). It is really 4 different types of instructions with 4 - 40 (or more) modes each for things like data size, addressing mode and so on. It is complex.
While RISC is typically a LOAD/STORE architecture. There is one instruction to LOAD from memory, another to STORE to memory. There are usually not many register to register instructions, and they are usually discrete instructions -- and there are no memory to memory instructions. There are fewer modes, and so on. The implementation is much simpler for RISC, but it has many more instructions to do the same thing.
The RISC way radically simplifies the implementation -- but can mean that you have 2, 3, or more different instructions to do the same thing as CISC. So anyone that starts getting into the reduced instruction COUNT argument of RISC is either oversimplifying (to the point of stupidity), they are ignorant of the topic, or they are intentionally deceiving others.
The P6-Core
When Intel implemented the P6-Core (PentiumPro), they needed to get the features of RISC (superscalar, pipelining, cache, etc.) without actually redesigning the instruction set. So they bolted it on. They have all the ugly x86 instructions decomposed into RISC like instructions (called ROps). Then it basically runs those instructions in a RISC-like sub-core. Think of it as built-in x86 emulation (1).
(1) Which is an interesting irony -- right now the two fastest x86 processors are the DEC/Compaq Alpha (running x86 in software emulation) and then the P6 Core based Pentiums (which run x86 in hardware emulation). Soon the AMD K7 will be out (and will probably be the fastest x86), and guess what -- it is really an Alpha-core (thanks to all the designers who left DEC to go to AMD) and it has an x86 front end on it (like the P6 but with a better backend). Even the PowerPC is getting close to beating the best Pentium-for-portables via emulation.
Why it isn't RISC?
- Bolting a RISC onto a CISC isn't really RISC.
Remember the P6 (and PentiumII, Celerons and PentiumIII)
still runs the ugly old x86 CISC instruction set that it
always has. So there are no RISC advantages for
modernizing the instruction set. Programmers still have
problems with a register starved architecture, and an
ugly outdated instruction set that can't do many things
they need (easily). They still have this butt-ugly stack
based floating point unit. You can't access the ROps
directly (and get around the CISC emulator/core). The
implementation of that RISC-like core is hidden (opaque)
from programmers, and changes implementation to
implementation -- so it is harder to properly schedule
things and difficult to optimize well, and anything you
do (programmers) are dependent on that implementation of
the chip.
- Which brings up another
point. If you optimize for the Pentium, you get worse
results on the P6 variants. If you optimize for the
P6, then you get worse Pentium (P5 or P55C)
performance, and worse still on the many other chips
out there (AMDs, CYRIX and so on). Really you have to
optimize for the individual processor variant to get
the best results. All the disadvantages of RISC (but
worse), without the advantages.
- Which brings up another
point. If you optimize for the Pentium, you get worse
results on the P6 variants. If you optimize for the
P6, then you get worse Pentium (P5 or P55C)
performance, and worse still on the many other chips
out there (AMDs, CYRIX and so on). Really you have to
optimize for the individual processor variant to get
the best results. All the disadvantages of RISC (but
worse), without the advantages.
- The design philosophy of the processor didn't change.
Intel didn't reduce the instruction set complexity --
they just bolted more on. Think of sticking a V8 motor,
bigger tires, and a camper-shell on an old Volkswagen
Beetle and calling it a SUV (Sport Utility Vehicle) --
that's Intel's way of approaching processor design. The
bolt-on RISC core (and CISC emulator) makes their chips
bigger, hotter, and use more power. They aren't easier to
design, but harder. They don't use less power, in fact
more. They have more bugs since they are rushed to market
(to try to keep up) which has been proven with Pentium
floating-point bugs, and P6 Overflow Bugs, all the
support chip bugs, and so on. Intel just throws 10 times
more designers on the problem, and pretends that makes up
for the lousy architecture. In reality they can almost
keep up, and their superior process technology helped,
but the complexity is in there. They didn't engineer
anything out, they didn't design (which is the RISC
philosophy) -- they just hacked more crap on and called
it "good enough".
- Even when you look at the RISC-like core, you realize
it isn't really a good RISC. They didn't have room to
make a lot of superscalar (parallel execution units), so
secondary units are usually stripped down units that only
work on some subset of functionality. Branch prediction
was pretty good. The pipes are deep but expensive -- they
had to go very deep just to improve anything -- and then
they have large stall penalties. They have to run the
processor fast (MHz), just to keep up with slower RISC
chips. They have small caches (because they couldn't
afford more room). They don't have a load/store
architecture, and so on.
- Intel didn't gain in faster Time-to-market. Intel promised that they would change processor Core (the engine that interprets instructions) every two years. That was 1995. By 1997 they should have had a second Core -- instead they stuffed MMX on the P6, added a backside cache and called it the PentiumII. Hmmm, definitely not what they promised. Now 1999 has come, and now we are getting the PentiumIII, do you think that is a new core? It is the same old P6 core, but now has KNI (Katmai's New Instructions -- basically MMX for Floating Point) bolted on. They promise a real core change in a processor called Willamette, due in 2001 -- but we'll see. (Actually, with the AMD K7 beating them to market, Intel may actually finally deliver the promised core change). Intel is delivering a new core every 6 years, primarily because of the complexity of their chip.
Conclusion
Intel has done an amazing job of hacking on to an old dying architecture, and dragging it along kicking and screaming. Intel's process technology has always been cutting edge, and helped them keep up. But even there they are falling behind.
IBM has got Copper and SOI and .12µ process, Motorola is going copper (and .18µ and showing .1µ in the labs) -- Intel is back at .22µ and Aluminum -- and copper is still years away for them (not to mention SOI). Their processes are about to start falling behind. Intel used to make up for inefficiencies in the design by just having more designers. (Many problems with bad design can be fixed with brute force and enough bodies). But eventually that fails. IA64 has split their focus, and they've thrown tons of designers at that and it is years late (originally scheduled for like 1997 assuming it was the P7 that they were talking about -- now scheduled for end of 2000). McKinley will be the first usable version, and is scheduled for 2001 (somewhere around December 32nd). The next real x86 processor is Willamette -- again probably in 2001. And Intel's last few cores have had bugs -- I'd be very concerned about the next ones. Intel has a lot of issues coming up, and I'd be very concerned for them.
The point is that the P6 isn't really RISC. You don't program in RISC, you get none of the true benefits of RISC, and they didn't take any of the old garbage out -- it would be like trying to cure clutter by adding more things to a room. Breaking down CISC instructions into something smaller is nothing new -- that has been done since the late 70's and was called Microcode. So what if this Pentium's (P6) microcode is a little more like a RISC engine (and is more sophisticated) than previous microcodes -- that isn't a revolution and that isn't RISC. In fact the whole point of going to RISC was to eliminate microcode -- not create more of it. Splitting the processor into two halves (the New RISC half and the old CISC half) helped Intel achieve some goals (like speed) -- but they only achieve speed by spending lots of space (transistors, heat and die area) to get around the same performance as a PowerPC that is half their size (or less). That isn't the design goals of RISC, and it certainly doesn't have the same design philosophy. In fact the old CISC half just wasted space (power, heat, cost, complexity, time) in order to prevent the new RISC half from being a really good design. If Intel threw away the old CISC half, and went to real RISC, they could achieve more performance in less area, with less power consumption, less cost to manufacture, and less heat produced.
So the next time someone tells you the PentiumPro, PentiumII, Celeron or PentiumIII is RISC, you can chuckle knowingly, pat them on the head, and shoo them on their way -- they obviously just don't get RISC.
Remember, this article is about design philosophy -- and looks at the issues accordingly. In implementation and real-life things are a little grayer than in philosophy class. So read this with just a hint of pragmatism -- and realize what an amazing job that Intel has done of dragging that old ugly processor along.
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